The present invention relates to the field of integrated circuit products, and more specifically to a buffer circuit that consumes little power.
There is an increasing need to integrate more and more functions into integrated circuit products for lower system costs. The increase in complexity of systems implemented on a single chip requires a reduction of power consumption. Lower-power operation increases reliability and reduces system costs. In battery-operated systems, lower-power operation and lower-operating voltages are desirable to increase battery life. Chip power consumption depends on the operating voltage. The lower the operating supply voltage, the lower the power consumption in the chip. So, to reduce the power consumption in the chip, it is thus desirable to reduce the supply voltage to at least part of the chip. For example, for an integrated circuit chip made with 0.6 .mu.m CMOS technology, the supply voltage should be reduced from 5 V nominal to 3.3 V nominal.
Where the supply voltage is 3.3V, the buffer circuit is preferably designed to withstand 5V input at an input/output (I/O) node. For example, a typical buffer circuit designed with CMOS digital integrated technology has driver PMOS transistors coupled in series between a supply-voltage VDD and an input/output node. Over-voltage can occur when a voltage at its I/O node is higher than the buffer circuit supply-voltage VDD. When a 5 V input voltage appears at the I/O node, and VDD is 3.3 V (typical value), a driver PMOS transistor can turn on if the source-to-gate voltage is greater than the PMOS threshold voltage. Also, when a 5 V input voltage appears at the I/O node, a P+/N-well diode from the I/O node to an N-well underneath the PMOS transistors turns on. As a result, the diode is forward biased and current leaks from the I/O node to the N-well.
A need therefore remains for a simple and reliable buffer circuit that consumes little power. Such a circuit should also prevent problems such as high leakage and gate-oxide damage. Specifically, the circuit should tolerate a voltage at its I/O node that is higher than the circuit supply-voltage VDD. Also, such a circuit should be cost effective and require little space.